0-In Formal Verification Products Validate Complex National Semiconductor Bus Bridge Design
0-In's Assertion-Based Verification Suite Finds Design Problems not Detected by any Other Verification Method
SAN JOSE, Calif. - January 6, 2003 - Today 0-In Design Automation, the Assertion-Based Verification Company, announced that National Semiconductor Corporation has successfully used 0-In products to fully verify a complex bus bridge design before tape-out. The 0-In tools found several corner-case design bugs that were not detected by traditional methods. The thoroughness of the verification process yielded a chip that contained no problems with the bus bridge and that sampled to customers on first silicon.
Companion I/O Chip Presents Tough Verification Challenges
The Information Appliance Group at National Semiconductor designs chip sets that integrate a wide range of functions, including traditional x86 South Bridge buses, Super I/O and legacy features, USB host controllers and audio controllers. "With these complex designs, the number one challenge in verification is finding bugs early enough in the design that we are not impacting our schedule with bug corrections," said Gordon Mortensen, director of engineering for the Internet Appliance Group at National.
Mr. Mortensen's team recently completed an I/O companion chip for National's Geode™ family of processors. This chip contained about a million gates of logic, built around a new high-bandwidth streaming internal bus. The most difficult portion of the verification effort involved an internal bus bridge connecting this streaming bus to a more traditional legacy bus. Because of the complexity involved in translating data from one bus to the other, Mr. Mortensen explained, "bridging those two protocols is a difficult a part of the design and that's where the bugs would normally show up."
National Selects 0-In Assertion-Based Verification Suite
The project team selected several 0-In products, including 0-In Check and 0-In Search, to verify the chip more rapidly and more thoroughly than with traditional methods. The developers added more than 5000 assertion checkers from the 0-In CheckerWare library to capture their design intent easily and quickly. They used 0-In Check to run these checkers in both block-level and chip-level simulations, detecting bugs at the source and measuring verification thoroughness. "We found errors as simple as a FIFO being de-qued incorrectly, up to things that were very complicated, such as corner-case bugs that were extremely difficult to see with a focused test written by an engineer," said Mr. Mortensen.
Dynamic Formal Verification Stress-Tests a Bus Bridge
Because of the high level of complexity in the bus bridge, the National engineers decided to use 0-In Search to stress all the corner cases. The team worked with 0-In to develop custom CheckerWare protocol monitors for both the streaming and legacy buses. These monitors provided the necessary rules for dynamic formal verification to expand upon the behaviors exercised in simulation, finding several critical bugs that were not detected with test cases. "The most interesting bug that we found was a corner-case condition on a coherent memory transaction. We did not see that when we were running targeted tests in simulation, but 0-In Search was successful at flagging that condition as a problem," reported Mr. Mortensen.
Silicon Results Confirm Value of 0-In Products
The effectiveness of dynamic formal verification and the entire assertion-based verification flow was confirmed when the I/O chip was fabricated and tested in the lab. Mr. Mortensen concluded, "We have not found any bugs on silicon with the bus-bridging module, but I am quite confident that we had some bugs identified using 0-In Search that had a high probability of making it into silicon. We had a very successful project with initial silicon sampled by our customers."
About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle - from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.
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Editorial Contacts:
0-In Design Automation
Steve White, 408-487-3649, swhite@0-in.com
Cayenne Communication
Linda Marchant, 919-683-9545, linda.marchant@cayennecom.com
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